1. Field of the Invention
The present invention is generally directed to packet-based communication links and, more particularly, to an input/output communication link that uses one or more control signals to negotiate a width of the communication link.
2. Description of the Related Art
FIG. 1 depicts a traditional personal computer (PC) architecture 100 that partitions a computer system into various blocks. One feature of this prior art architecture is the use of the peripheral component interconnect (PCI) bus 101 as the connection between a “north bridge” integrated circuit 103 and a “south bridge” integrated circuit 105. The north bridge 103 functions generally as a switch connecting one or more central processing units (CPUs) 107, a graphics bus 109 (such as the accelerated graphics port (AGP) bus), the PCI bus 101 and main memory 111. The north bridge 103 also contains the memory controller function. The architecture also includes the “host bus” connection 108 between the north bridge 103 and the CPU 107.
The south bridge 105 provides an interface to various input/output (I/O) portions of the computer system 100 by providing a bridge function between the PCI bus 101 and legacy industry standard architecture (ISA) bus 115, an integrated device electronics (IDE) disk interface 117 and a universal serial bus (USB) 119. Other devices, buses and functions may also be included in the south bridge 105. In the illustrated prior art architecture, the PCI bus 101 also functions as a major I/O bus for add-in functions, such as network connection 121. The various buses and devices shown in FIG. 1 are conventional in the personal computer (PC) industry and are not described further herein.
Demand for increased system performance and the continuing increase in processor speeds has put pressure on system buses, such as the PCI bus and the host bus, to also provide better performance. However, configuration of some of the present buses, such as the multi-drop configuration of the PCI bus, tends to limit their performance. In an attempt to increase the performance of I/O buses, designers have designed various new bus architectures. For example, in the PCI Express (PCIe) architecture, a point-to-point topology was introduced. In this topology a shared switch replaces the shared bus of the PCI architecture. As such, in the PCIe architecture, each device has its own dedicated bus or link, which is composed of one or more lanes with each lane (i.e., a pair of send and receive signals) being capable of transmitting one bit at a time in both directions at the same time. At startup, PCIe devices negotiate with the switch to determine the maximum number of lanes for the link. The link width negotiation depends upon a maximum width of the link (i.e., an actual number of physical signal pairs), a width of an associated connector into which the device is plugged, a width of the device and a width of the switch interface. While the PCIe architecture allows for negotiating a maximum number of lanes for a link and splitting a link to facilitate different topologies, the PCIe architecture implements a relatively complex method for splitting a link that requires every lane to exchange identifying information serially at link initialization.
What is needed is a technique that allows connected devices to negotiate a width of an associated link that is relatively straightforward, easy to implement and readily allows for splitting a link to facilitate different topologies.